The present invention relates to a phase-locked loop (called PLL, hereinafter) circuit to be used for a frequency multiplier (that is, frequency synthesizer) or the like, for generating signals synchronized with input signals in phase and in particular to the improvement in a phase-locked lead-in circuit.
Conventional technologies rating to a PLL circuit are disclosed in JP-A-9-153797 (especially in FIGS. 1 and 4) and Howard M. Berlin, Keiichi Miyata and Fumi Tokuhushi, “PLL no Sekkei to Jitsuyou kairo (Design of PLL and Practical circuits)”, SeaStar, Apr. 1, 1992, especially in pgs. 1-3, 19-31, 49-50, 59-70 and 91.
Conventionally, as shown in FIG. 4 in JP-A-9-153797, a PLL circuit to be used in a frequency multiplier includes a phase comparator, a loop filter, a voltage controlled oscillator (called “VCO” hereinafter) and a frequency divider. The phase comparator compares phases of the index signal of a frequency fi and the reference signal of a frequency fr and generates the average output voltage (which is a direct current (DC) output voltage also called error voltage) in proportion to the phase difference Δφ (=fi−fr). The loop filter includes a low-pass filter (called “LPF” hereinafter) for smoothing the output voltage of the phase comparator. The VCO oscillates at a frequency f0 in accordance with the output voltage of the loop filter. The frequency divider divides the output signals of the VCO by a predetermined frequency-dividing rate N (where N is a positive integer), generates the reference signal and feedback-inputs the reference signal to the phase comparator.
In this kind of PLL circuit, the oscillation frequency f0 of the VCO is divided by the frequency-divider and becomes the reference signal of the frequency fr. The reference signal of the frequency fr is returned to the phase comparator, and is compared with the frequency fi of the index signal by the phase comparator. Then, an error voltage is output. The error voltage is an average direct current voltage in proportion to the frequency difference (fi−fr) and the phase difference Δφ of the index signal and reference signal. An influence of high-frequency noise is eliminated from the error voltage by the loop filter, and the result is returned to the VCO. Thus, the frequency f0 of the VCO varies so as to obtain lower frequency differences (fi−fr), and the loop enters a capture range state.
This processing is repeated until the frequency fr of the reference signal agrees with the frequency fi of the index signal and until the frequency difference (fi−fr) reaches zero. When the frequency fr and frequency fi agree, the loops are synchronized (that is, a phase-locked state). In the phase-locked state, the frequency f0 of the VCO is proportional to the frequency fi of the input index signal except for some finite phase differences. The phase difference is required for generating an error voltage required for shifting the frequency of the VCO so as to maintain the loops in the phase-locked state. Because of the repeated operation of the loop system in the phase-locked state, the output signal with N times of frequency rate in phase with the index signal in accordance with any changes in the index signal is output from an output terminal of the VCO.
As disclosed in “Design of PLL circuit and Practical circuit (pgs. 1 to 3), an entire range in which the loop system follows the change in frequency fi of the index signal is called a lock range. The lock range is wider than a frequency range (that is, capture range) in which the loops are in the phase-locked state. The dynamic characteristic of the PLL is basically controlled by the loop filter. When the frequency difference (fi−fr) of the index signal and reference signal is significantly large, the signal cannot pass through the loop filter due to the excessively high frequency. As a result, the signal is determined as being beyond the capture range of the loop, and the lock state is turned off. Once the loops enter the phase-locked state, the loop speed in accordance with the change in frequency fi of the index signal is only controlled by the loop filter. Additionally, even when the system is unlocked due to instance noise, the original signal can be captured since the loop filter has a short time memory ability.
However, as the unlocked time increases, the possibility to adversely affect on the loaded circuits connected to the output terminal of the VCO increases. In order to prevent this, a PLL circuit has been proposed which includes an unlock detecting circuit for detecting a phase unlock of the PLL circuit to turn on/off a PLL operation signal based on the detection signal.
When the frequency fi of the index signal is changed rapidly and significantly, the phase difference Δφ increases. Therefore, the oscillation frequency fo of the VCO changes great. Then, the stable time until the frequency fr of the reference signal agrees with the frequency fi of the index signal increases.
In order to prevent this, in the technology disclosed in JP-A-9-153797, as shown in FIG. 1, a limiter for limiting an output of the loop filter is provided between the loop filter and the VCO. Furthermore, a limit-value control circuit is provided therebetween for controlling the limit voltage value of the limiter in accordance with the change in frequency of the index signal.
However, conventional PLL circuits have problems mentioned in (1) and (2) below.
(1) Problems of PLL Circuit Having Unlock Detecting Circuit
A response characteristic of the PLL circuit is mainly determined by the characteristic of the loop filter. In order to operate the PLL circuit in a stable manner, the frequency pass range of the loop filter is generally set lower. However, in this case, the response to the change in reference signal may be delayed and/or the time for phase lead-in may be increased. When the frequency pass range of the loop filter is set higher in order to increase the response speed, the phase change (jitter) of the output signal is increased, which is a problem. Furthermore, when the frequency rate of the output signal and the index signal (that is, the frequency-dividing rate N of the frequency divider) increases, the phase lead-in time is difficult to be reduced.
In this way, the conventional PLL circuits have problems like a longer time for the phase lead-in at the beginning of the PLL operation. This problem becomes significant especially in the PLL circuit in which the active/inactive (that is, closed loop control/open loop control) are switched frequently by using the unlock detecting circuit.
(2) Problems of PLL Circuit Having Limiter
The stable time of the PLL circuit may be reduced, but no measures have been taken for unlocking. Furthermore, since a limit value control circuit is required for switching limit voltages of the limiter, the circuit construction becomes more complicated, which is another problem.